Fault-aware Pareto Frontier Exploration for Dependable System Architectures

While designing dependable systems, a large number of asset combinations (system configurations) with contrary quality objectives needs to be investigated. Basically, each feasible configuration should be investigated. For fault-tolerant embedded systems this problem is extended by anticipating hardware faults leading to changed deployments of stressed resources in redundant constellations. The identification and evaluation of the best-fitting configuration remains a computationally intensive and difficult task at all. We propose a multi-stage approach (1) to sample Paretooptimal configurations for redundant system designs within hostile environments, (2) to check satisfiability of structural constraints and (3) to measure and identify quality degradation in fault scenarios. Thus, allowing developers to identify design flaws, leading to large quality degradations in case of emerging faults. We use genetic algorithms (NSGA-II) for sampling a wide range of system designs and demonstrate our approach by means of an exemplary fault-tolerant system.